ST STM32F301 6 Series Reference Manual page 399

RM0366
17.4.5 TIM1 status register (TIM1_SR)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF
rc_w0
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 CC6IF: Compare 6 interrupt flag
Bit 16 CC5IF: Compare 5 interrupt flag
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
Bit 8 B2IF: Break 2 interrupt flag
Bit 7 BIF: Break interrupt flag
28 27 26 25
Res. Res. Res.
12 11 10 9
rc_w0 rc_w0 rc_w0
Refer to CC1IF description (Note: Channel 6 can only be configured as output)
Refer to CC1IF description (Note: Channel 5 can only be configured as output)
Refer to CC1OF description
Refer to CC1OF description
Refer to CC1OF description
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by
software if the break 2 input is not active.
0: No break event occurred.
1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1
in the TIMx_DIER register.
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in
the TIMx_DIER register.
24 23 22
Res. Res. Res.
8 7 6
B2IF BIF TIF COMIF
rc_w0 rc_w0 rc_w0 rc_w0
RM0366 Rev 5
Advanced-control timer (TIM1)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
CC4IF CC3IF CC2IF
rc_w0 rc_w0 rc_w0
17 16
CC6IF CC5IF
rc_w0 rc_w0
1 0
CC1IF UIF
rc_w0 rc_w0
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