ST STM32F301 6 Series Reference Manual page 465

RM0366
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–
–
–
2. Configure the channel 1 as follows, to detect rising edges on TI:
–
–
–
–
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Counter clock = CK_CNT = CK_PSC
18.3.19 Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 192: Master/Slave timer example
with 1 channel only timers
selection blocks.
ETF = 0000: no filter
ETPS=00: prescaler disabled
ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
IC1F=0000: no filter.
The capture prescaler is not used for triggering and does not need to be
configured.
CC1S=01in TIMx_CCMR1 register to select only the input capture source
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edge only).
Figure 191. Control circuit in external clock mode 2 + trigger mode
TI1
CEN/CNT_EN
ETR
Counter register
TIF
present an overview of the trigger selection and the master mode
34
and Figure 193: Master/slave connection example
RM0366 Rev 5
General-purpose timer (TIM2)
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MS33110V1
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