ST STM32F301 6 Series Reference Manual page 867

RM0366
31 Revision history
Date
23-Apr-2014
09-Sep-2014
23-Jun-2015
Table 128. Document revision history
Revision
1 Initial release.
Reset and clock control (RCC) section
– Updated Section 7.4.8: APB1 peripheral clock enable register
(RCC_APB1ENR), Section 7.4.5: APB1 peripheral reset register
(RCC_APB1RSTR), Section 7.4.13: Clock configuration register 3
(RCC_CFGR3) and Section 7.4.14: RCC register map.
System configuration controller (SYSCFG) section
– Updated Section 9.1.7: SYSCFG configuration register 2
2
(SYSCFG_CFGR2) and Section 9.1.10: SYSCFG register map
Analog-digital converters (ADC) section
– Table 42: ADC1 (master) & 2 (slave) - External triggers for regular
channels,
– Table 43: ADC1 & ADC2 - External trigger for injected channels,
– Figure 85: VBAT channel block diagram
Updated the following sections:
Advanced-control timers (TIM1), General-purpose timers
(TIM2/TIM3/TIM4/TIM15/16/17)
– Section 19.6.16: TIM15 break and dead-time register
(TIM15_BDTR),
– Section 19.6.13: TIM16&TIM17 break and dead-time register
(TIMx_BDTR),
– Section 19.6.17: TIM16&TIM17 register map,
– ETF[3:0] description in Section 17.4.3: TIM1 slave mode control
register (TIMx_SMCR), Section 18.4.3: TIM2 slave mode control
register (TIM2_SMCR)(TIM3_SMCR)(TIMx_SMCR)N/A
– C1F[3:0] description in Section 17.4.7: TIM1 capture/compare mode
register 1 (TIMx_CCMR1), Section 18.4.7: TIM2 capture/compare
mode register 1 (TIM2_CCMR1)(TIM3_CCMR1)(TIMx_CCMR1)N/A,
3 Section 19.6.8: TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1)
– BK2F3:0] and BKF[3:0} description in Section 17.4.18: TIM1 break
and dead-time register (TIMx_BDTR).
Reset and Clock (RCC)
– the bit field for MCOPRE in Section 7.4.2: Clock configuration
register (RCC_CFGR),
– Bits [32:16] description in Section 7.4.13: Clock configuration
register 3 (RCC_CFGR3),
Universal synchronous asynchronous receiver transmitter
(USART)
– Section 26: Universal synchronous/asynchronous receiver
transmitter (USART/UART): addition of 0.5 stop bit in smartcard
mode, addition of TCBGT bit in USARTx_CR3 and USARTx_ISR
registers, addition of TCGBTCF bit in USARTx_ICR register.
RM0366 Rev 5
Revision history
Changes
867/874
870