ST STM32F301 6 Series Reference Manual page 847

RM0366
Bit
4:3
5
6
7
Refer to the Cortex
registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.
Bit
0..2
The ACK Response must be followed by a turnaround time only if it is a READ transaction
or if a WAIT or FAULT acknowledge has been received.
Bit
0..31
32
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
28.8.3 SW-DP state machine (reset, idle states, ID code)
The State Machine of the SW-DP has an internal ID code, which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default Arm
0x1BA01477 (corresponding to Cortex
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
•
The SW-DP state machine is in RESET STATE either after power-on reset, or after the
DP has switched from JTAG to SWD or after the line is high for more than 50 cycles
•
The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.
• After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target issues a FAULT
acknowledge response on another transactions.
Table 117. Packet request (8-bits) (continued)
Name
A(3:2) Address field of the DP or AP registers (refer to
Parity Single bit parity of preceding bits
Stop 0
Not driven by the host. Must be read as "1" by the target because of
Park
the pull-up
®
-M4F r0p1 TRM for a detailed description of DPACC and APACC
Table 118. ACK response (3 bits)
Name
001: FAULT
ACK 010: WAIT
100: OK
Table 119. DATA transfer (33 bits)
Name
WDATA or RDATA Write or Read data
Parity Single parity of the 32 data bits
RM0366 Rev 5
Description
Description
Description
®
-M4F r0p1).
Debug support (DBG)
Table 116)
®
one and is set to
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