ST STM32F301 6 Series Reference Manual page 209

RM0366
ADC state
JADSTART
ADSTART
ADSTP
ADC_DR
ADC state
JADSTART
JADSTP
ADC_JDR
ADSTART
ADC_DR
Figure 32. Stopping ongoing regular conversions
Trigger
RDY
Set
by SW
(software is not allowed to configure regular conversions selection and triggers)
Data N-2
Figure 33. Stopping ongoing regular and injected conversions
Regular trigger
RDY
Set by
INJECTED CONVERSIONS ongoing
SW
(software is not allowed to configure injected conversions selection and triggers)
Set by
SW
(software is not allowed to configure regular conversions selection and triggers)
ADSTP
DATA N-2
Sample Convert
Ch(N-1) Ch(N-1)
REGULAR CONVERSIONS
ongoing
Injected trigger
Sample Convert
RDY
Ch(N-1) Ch(N-1)
DATA M-1
REGULAR CONVERSIONS ongoing
RM0366 Rev 5
Analog-to-digital converters (ADC)
Trigger
Sample
RDY
C
Ch(N)
Set
by
SW
Data N-1
Regular trigger
Sample
C RDY Sampl RDY
Ch(M)
Cleared
by HW
Cleared
Set by
by HW
SW
Cleared
by HW
Set by
Cleared
SW
by HW
DATA N-1
RDY
Cleared
by HW
Cleared
by HW
MS30533V2
MS30534V1
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