ST STM32F301 6 Series Reference Manual page 521

RM0366
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The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set.
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If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until it is written with 1 again. In this case, it can be used for
security and the break input can be connected to an alarm from power drivers, thermal
sensors or any security components.
Note: If the MOE is reset by the CPU while the AOE bit is set, the outputs are in idle state and
forced to inactive level or Hi-Z depending on OSSI value.
If both the MOE and AOE bits are reset by the CPU, the outputs are in disabled state and
driven with the level programmed in the OISx bit in the TIMx_CR2 register.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows the configuration
of several parameters to be freezed (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). The protection can be
selected among 3 levels with the LOCK bits in the TIMx_BDTR register. Refer to
Section 19.6.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) on
page 569. The LOCK bits can be written only once after an MCU reset.
The Figure 223
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
If OSSI=0 then the timer releases the enable outputs (taken over by the GPIO
which forces a Hi-Z state) else the enable outputs remain or become high as soon
as one of the CCxE or CCxNE bits is high.
shows an example of behavior of the outputs in response to a break.
General-purpose timers (TIM15/TIM16/TIM17)
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