ST STM32F301 6 Series Reference Manual page 346

Advanced-control timer (TIM1)
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
Figure 108. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow
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Figure 107. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
0003
(UIF)
CK_PSC
CNT_EN
0034
(UIF)
RM0366 Rev 5
0002 0001 0000
0035
RM0366
0001 0002 0003
MS31190V1
0036 0035
MS31191V1