ST STM32F301 6 Series Reference Manual page 397

RM0366
Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (refer to ETP bit in TIMx_SMCR for tim_etr_in and
CCxP/CCxNP bits in TIMx_CCER register for tim_ti1fp1 and tim_ti2fp2).
0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal
clock.
0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
reinitializes the counter, generates an update of the registers and starts the counter.
Codes above 1000: Reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
Slave TIM
TIM1
1. TIM1_ITR3 selection is made using bit 6 of the SYSCFG_CFGR1 register.
17.4.4 TIM1 DMA/interrupt enable register
(TIM1_DIER)
Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. TDE COMDE CC4DE CC3DE CC2DE CC1DE
rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from
the master timer.
Table 60. TIM1 internal trigger connection
ITR0 (TS = 000)
TIM15
12 11 10 9
rw rw rw rw
ITR1 (TS = 001)
TIM2
8 7 6
UDE BIE TIE COMIE CC4IE
rw rw rw
RM0366 Rev 5
Advanced-control timer (TIM1)
ITR2 (TS = 010) ITR3 (TS = 011)
Reserved TIM17 OC1
5 4 3 2
CC3IE CC2IE
rw rw rw rw
(1)
1 0
CC1IE UIE
rw rw
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