ST STM32F301 6 Series Reference Manual page 166

Direct memory access controller (DMA)
Bit 8 GIF3: Global interrupt flag for channel 3
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 7 TEIF2: Transfer error (TE) flag for channel 2
0: No TE event
1: A TE event occurred.
Bit 6 HTIF2: Half transfer (HT) flag for channel 2
0: No HT event
1: An HT event occurred.
Bit 5 TCIF2: Transfer complete (TC) flag for channel 2
0: No TC event
1: A TC event occurred.
Bit 4 GIF2: Global interrupt flag for channel 2
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
Bit 3 TEIF1: Transfer error (TE) flag for channel 1
0: No TE event
1: A TE event occurred.
Bit 2 HTIF1: Half transfer (HT) flag for channel 1
0: No HT event
1: An HT event occurred.
Bit 1 TCIF1: Transfer complete (TC) flag for channel 1
0: No TC event
1: A TC event occurred.
Bit 0 GIF1: Global interrupt flag for channel 1
0: No TE, HT, or TC event
1: A TE, HT, or TC event occurred.
10.6.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.
166/874 RM0366 Rev 5
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