ST STM32F301 6 Series Reference Manual page 538

General-purpose timers (TIM15/TIM16/TIM17)
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
19.5.5 TIM15 status register (TIM15_SR)
Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
Bit 8 Reserved, must be kept at reset value.
538/874
12 11 10 9
Res. CC2OF CC1OF
rc_w0 rc_w0
Refer to CC1OF description
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
8 7 6
Res. BIF TIF COMIF
rc_w0 rc_w0 rc_w0
RM0366 Rev 5
5 4 3 2
Res. Res. CC2IF
rc_w0
RM0366
1 0
CC1IF UIF
rc_w0 rc_w0