ST STM32F301 6 Series Manuals
Manuals and User Guides for ST STM32F301 6 Series. We have 1 ST STM32F301 6 Series manual available for free PDF download: Reference Manual
ST STM32F301 6 Series Reference Manual (874 pages)
advanced Arm-based 32-bit MCUs
Brand: ST
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Category: Microcontrollers
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Size: 11 MB
Table of Contents
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Glossary37
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S0: I-Bus39
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S1: D-Bus39
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S2: S-Bus39
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S3: DMA-Bus39
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Busmatrix39
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Introduction40
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Page Erase51
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Mass Erase52
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Introduction68
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Stop Mode83
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Standby Mode84
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Reset90
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Power Reset90
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System Reset90
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Clocks92
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HSE Clock94
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HSI Clock95
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Pll96
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LSE Clock96
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LSI Clock97
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ADC Clock98
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RTC Clock98
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I2S Clock99
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Low-Power Modes100
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RCC Registers102
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RCC Register Map124
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Offset Register125
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Introduction126
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GPIO Registers136
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SYSCFG Registers144
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(Syscfg_Exticr1)146
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(Syscfg_Exticr2)147
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(Syscfg_Exticr3)148
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(Syscfg_Exticr4)149
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Introduction152
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Dma1153
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DMA Transfers157
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DMA Arbitration158
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DMA Channels158
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DMA Interrupts164
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DMA Registers164
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DMA Register Map172
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Main Features179
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Block Diagram179
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EXTI Registers183
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Introduction193
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Clocks196
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Timing207
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Jextsel, Jexten)210
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Data Management226
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ADC Interrupts243
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ADC Register Map274
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Introduction278
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DAC Data Format280
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Noise Generation283
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DMA Request285
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DMA Underrun285
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DAC Registers286
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(Dac_Dhr12L1)289
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DAC Register Map291
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Introduction292
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COMP Interrupts296
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COMP Registers296
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Clock303
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Calibration304
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OPAMP Modes306
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OPAMP Registers309
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Offset Register312
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Introduction313
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Reset and Clocks317
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Max Count Error319
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Acquisition Mode320
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TSC Interrupts321
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TSC Registers321
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(Tsc_Ioascr)326
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TSC Register Map329
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Time-Base Unit335
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Counter Modes337
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Clock Selection351
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PWM Input Mode359
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PWM Mode361
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One-Pulse Mode377
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DMA Burst Mode389
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Debug Mode390
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TIM1 Registers391
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(Tim1_Smcr)395
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(Tim1_Dier)397
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(Tim1_Ccmr1)403
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(Tim1_Ccmr2)407
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(Tim1_Ccer)408
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(Tim1_Ccr1)413
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(Tim1_Ccr2)414
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(Tim1_Ccr3)414
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(Tim1_Ccr4)415
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(Tim1_Bdtr)415
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(Tim1_Dcr)418
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(Tim1_Dmar)419
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(Tim1_Ccmr3)420
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(Tim1_Ccr5)421
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(Tim1_Ccr6)422
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Time-Base Unit428
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Counter Modes430
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Clock Selection440
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PWM Input Mode447
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PWM Mode450
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One-Pulse Mode457
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DMA Burst Mode470
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Debug Mode471
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TIM2 Registers472
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(Tim2_Ccer)487
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Time-Base Unit500
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Counter Modes502
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Clock Selection507
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PWM Mode515
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One-Pulse Mode524
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DMA Burst Mode530
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Debug Mode532
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TIM15 Registers533
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(Tim15_Ccmr1)542
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Time-Base Unit576
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Counting Mode578
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Clock Source581
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Debug Mode582
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TIM6 Registers582
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Introduction589
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Debug Mode592
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WWDG Interrupts592
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WWDG Registers592
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Introduction595
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Window Option596
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Debug Mode597
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IWDG Registers598
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Introduction604
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Tamper Detection618
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Alarm Output620
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RTC Interrupts620
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RTC Registers621
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(Rtc_Tafcr)640
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RTC Register Map645
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Introduction648
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Noise Filters652
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I2C Reset656
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I2C Target Mode659
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Bus Protocols681
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Error Conditions694
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Bus Error (BERR)694
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I2C Interrupts696
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I2C DMA Requests697
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I2C Debug Modes697
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I2C Registers698
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I2C Register Map711
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Introduction712
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Break Characters721
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Idle Characters721
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USART Receiver721
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Break Character723
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Idle Character723
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Overrun Error724
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Framing Error727
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Block Mode (T=1)744
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Using USART750
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USART Interrupts754
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USART Registers756
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Introduction780
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Data Packing793
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Packing with DMA795
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SPI Status Flags801
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SPI Error Flags802
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NSS Pulse Mode803
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TI Mode803
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CRC Calculation804
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CRC Principle804
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SPI Interrupts806
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I2S Full Duplex808
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Figure 323. I811
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Clock Generator817
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Figure 338. I817
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I 2 S Slave Mode821
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I2S Status Flags823
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I2S Error Flags824
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DMA Features825
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I2S Interrupts825
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Overview837
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M4F Tap844
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JTAG Debug Port844
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SW Debug Port846
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SW-DP Registers848
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SW-AP Registers849
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Core Debug850
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854854
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TPUI Formatter859
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DBG Register Map863
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Revision History867
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