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ST STM32F301 6 Series Reference Manual page 644

Advanced arm-based 32-bit mcus

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Real-time clock (RTC)
24.6.18
RTC alarm B sub second register (RTC_ALRMBSSR)
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization
mode.
This register is write protected.The write access procedure is described in
register write
Address offset: 0x48
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
Bits 23:15
Bits 14:0 SS[14:0]: Sub seconds value
644/874
protection.
28
27
26
25
MASKSS[3:0]
rw
rw
rw
12
11
10
9
rw
rw
rw
rw
0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
0x1: SS[14:1] are don't care in Alarm B comparison. Only SS[0] is compared.
0x2: SS[14:2] are don't care in Alarm B comparison. Only SS[1:0] are compared.
0x3: SS[14:3] are don't care in Alarm B comparison. Only SS[2:0] are compared.
...
0xC: SS[14:12] are don't care in Alarm B comparison. SS[11:0] are compared.
0xD: SS[14:13] are don't care in Alarm B comparison. SS[12:0] are compared.
0xE: SS[14] is don't care in Alarm B comparison. SS[13:0] are compared.
0xF: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Reserved, must be kept at reset value.
This value is compared with the contents of the synchronous prescaler counter to determine
if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
24
23
22
Res.
Res.
rw
8
7
6
SS[14:0]
rw
rw
rw
RM0366 Rev 5
Section : RTC
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
rw
rw
rw
w
RM0366
17
16
Res.
Res.
1
0
rw
rw

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