ST STM32F301 6 Series Reference Manual page 682

Inter-integrated circuit interface (I2C)
For more details on these protocols, refer to the SMBus specification (http://smbus.org).
STM32CubeMX implements an SMBus stack thanks to X-CUBE-SMBUS, a downloadable
software pack that allows basic SMBus configuration per I2C instance.
Address resolution protocol (ARP)
SMBus target address conflicts can be resolved by dynamically assigning a new unique
address to each target device. To provide a mechanism to isolate each device for the
purpose of address assignment, each device must implement a unique 128-bit device
identifier (UDID). In the I2C peripheral, it is implemented by software.
The I2C peripheral supports the Address resolution protocol (ARP). The SMBus device
default address (0b1100 001) is enabled by setting the SMBDEN bit of the I2C_CR1
register. The ARP commands must be implemented by the user software.
Arbitration is also performed in target mode for ARP support.
For more details on the SMBus address resolution protocol, refer to the SMBus specification
(http://smbus.org).
Received command and data acknowledge control
An SMBus receiver must be able to NACK each received command or data. In order to
allow the ACK control in target mode, the target byte control mode must be enabled, by
setting the SBC bit of the I2C_CR1 register. Refer to
details.
Host notify protocol
To enable the host notify protocol, set the SMBHEN bit of the I2C_CR1 register. The I2C
peripheral then acknowledges the SMBus host address (0b0001 000).
When this protocol is used, the device acts as a controller and the host as a target.
SMBus alert
The I2C peripheral supports the SMBALERT# optional signal through the SMBA pin. With
the SMBALERT# signal, an SMBus target device can signal to the SMBus host that it wants
to talk. The host processes the interrupt and simultaneously accesses all SMBALERT#
devices through the alert response address (0b0001 100). Only the device/devices which
pulled SMBALERT# low acknowledges/acknowledge the alert response address.
When the I2C peripheral is configured as an SMBus target device (SMBHEN = 0), the
SMBA pin is pulled low by setting the ALERTEN bit of the I2C_CR1 register. The alert
response address is enabled at the same time.
When the I2C peripheral is configured as an SMBus host (SMBHEN = 1), the ALERT flag of
the I2C_ISR register is set when a falling edge is detected on the SMBA pin and ALERTEN
= 1. An interrupt is generated if the ERRIE bit of the I2C_CR1 register is set. When
ALERTEN = 0, the alert line is considered high even if the external SMBA pin is low.
Note: If the SMBus alert pin is not required, keep the ALERTEN bit cleared. The SMBA pin can
then be used as a standard GPIO.
Packet error checking
A packet error checking mechanism introduced in the SMBus specification improves
reliability and communication robustness. The packet error checking is implemented by
682/874
Target byte control mode
RM0366 Rev 5
RM0366
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