ST STM32F301 6 Series Reference Manual page 39

RM0366
2.1.1 S0: I-bus
This bus connects the instruction bus of the Cortex
used by the core to fetch instructions. The targets of this bus are the internal Flash memory
and the SRAM up to 16 Kbytes.
2.1.2 S1: D-bus
This bus connects the DCode bus (literal load and debug access) of the Cortex
the BusMatrix. The targets of this bus are the internal Flash memory and the SRAM (16
Kbytes).
2.1.3 S2: S-bus
This bus connects the system bus of the Cortex
used to access data located in the peripheral or SRAM area. The targets of this bus are the
SRAM (16 Kbytes), the AHB to APB1/APB2 bridges, the AHB IO port and the ADC.
2.1.4 S3: DMA-bus
This bus connects the AHB master interface of the DMA to the BusMatrix, which manages
the access of different Masters to flash, SRAM, and peripherals.
2.1.5 BusMatrix
The BusMatrix manages the access arbitration between Masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of five masters (CPU AHB, System
bus, DCode bus, ICode bus, DMA1 bus) and seven slaves (FLITF, SRAM, AHB2GPIO and
AHB2APB1/2 bridges, and ADC).
AHB/APB bridges
The two AHB/APB bridges provide full synchronous connections between the AHB and the
two APB buses. APB1 is limited to 36 MHz. APB2 operates at full speed (72 MHz).
Refer to
peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral the user has to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
Section 2.2: Memory organization on page 40
®
-M4 core to the BusMatrix. This bus is
®
-M4 core to the BusMatrix. This bus is
RM0366 Rev 5
System and memory overview
for the address mapping of the
®
-M4 core to
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