ST STM32F301 6 Series Reference Manual page 60

Embedded flash memory
3.5.5 Flash control register (FLASH_CR)
Address offset: 0x10
Reset value: 0x0000 0080
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
OBL_L
Res. Res. AUNC EOPIE
H
rw rw
Bits 31:14 Reserved, must be kept at reset value.
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Bit 2 PGERR: Programming error
Set by hardware when an address to be programmed contains a value different
from '0xFFFF' before programming.
Reset by writing 1.
Note: The STRT bit in the FLASH_CR register should be reset before starting a
programming operation.
Bit 1 Reserved, must be kept at reset value.
Bit 0 BSY: Busy
This indicates that a Flash operation is in progress. This is set on the beginning
of a Flash operation and reset when the operation finishes or when an error
occurs.
27 26 25
Res. Res. Res.
11 10 9
OPTWR
Res. ERRIE
E
rw rw
Bit 13 OBL_LAUNCH: Force option byte loading
When set to 1, this bit forces the option byte reloading. This operation generates
a system reset.
0: Inactive
1: Active
Bit 12 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR
register goes to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bit 11 Reserved, must be kept at reset value.
Bit 10 ERRIE: Error interrupt enable
This bit enables the interrupt generation on an error when PGERR /
WRPRTERR are set in the FLASH_SR register.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bit 9 OPTWRE: Option bytes write enable
When set, the option bytes can be programmed. This bit is set on writing the
correct key sequence to the FLASH_OPTKEYR register.
This bit can be reset by software
Bit 8 Reserved, must be kept at reset value.
24 23 22
Res. Res. Res.
8 7 6
Res. LOCK STRT OPTER
rw rw
RM0366 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OPT
Res. MER
PG
rw rw rw
RM0366
17 16
Res. Res.
1 0
PER PG
rw rw