ST STM32F301 6 Series Reference Manual page 655

RM0366
Note: t and t
AF(min)
the device datasheet for t
The t
HD;DAT
0.45 µs for Fast-mode Plus. It must be lower than the maximum of t
time. This maximum must only be met if the device does not stretch the LOW period (t
of the SCL signal. When it stretches SCL, the data must be valid by the set-up time before it
releases the clock.
The SDA rising edge is usually the worst case. The previous condition then becomes:
SDADEL ≤ {t
Note: This condition can be violated when NOSTRETCH = 0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL[3:0] value.
After t
SDADEL
the data was not yet written in I2C_TXDR register, the SCL line is kept at low level during
the setup time. This setup time is
t = (PRESC + 1) x t
PRESC
To bridge the undefined region of the SDA transition (rising edge usually worst case), the
user must program SCLDEL[3:0] so as to fulfill the following condition:
{[t + t
r (max)
Refer to the following table for t
Use the SDA and SCL real transition time values measured in the application to widen the
scope of allowed SDADEL[3:0] and SCLDEL[3:0] values. Use the maximum SDA and SCL
transition time values defined in the standard to make the device work reliably regardless of
the application.
Note: At every clock pulse, after SCL falling edge detection, I2C operating as controller or target
stretches SCL low during at least
transmission and reception modes. In transmission mode, if the data is not yet written in
I2C_TXDR when SDA delay elapses, the I2C peripheral keeps stretching SCL low until the
next data is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
When the NOSTRETCH bit is set in target mode, the SCL is not stretched. The
SDADEL[3:0] must then be programmed so that it ensures a sufficient setup time.
Table 85. I²C-bus and SMBus specification data setup and hold times
Symbol Parameter
t Data hold time
HD;DAT
t Data valid time
VD;DAT
t Data setup time
SU;DAT
Rise time of both
t
r
SDA and SCL signals
Fall time of both
t
f
SDA and SCL signals
are only part of the condition when the analog filter is enabled. Refer to
AF(max)
values.
AF
time can at maximum be 3.45 µs for Standard-mode, 0.9 µs for Fast-mode, and
- t - t
VD;DAT (max) r (max)
, or after sending SDA output when the target had to stretch the clock because
. t
I2CCLK SCLDEL
] / [(PRESC + 1) x t
SU;DAT (min)
Standard-mode
(Sm)
Min Max
0
- 3.45
250
- 1000
-
Inter-integrated circuit interface (I2C)
- [(DNF + 4) x t
AF (max) I2CCLK
t = (SCLDEL + 1) x t
SCLDEL
impacts the setup time
]} - 1 ≤ SCLDEL
I2CCLK
, t , t , t , and t
f r HD;DAT VD;DAT
[(SDADEL + SCLDEL + 1) x (PRESC + 1) + 1] x t
Fast-mode
(Fm)
Min Max
- 0 -
- 0.9
- 100 -
- 300
300 - 300
RM0366 Rev 5
by a transition
VD;DAT
]} / {(PRESC + 1) x t
I2CCLK
, where
PRESC
t .
SU;DAT
standard values.
SU;DAT
Fast-mode Plus
SMBus
(Fm+)
Min Max Min
0 - 0.3
- 0.45 -
50 - 250
- 120 -
- 120 -
)
LOW
}
, in both
I2CCLK
Unit
Max
-
µs
-
-
1000
ns
300
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