ST STM32F301 6 Series Reference Manual page 810

Serial peripheral interface / integrated interchip sound (SPI/I2S)
Data are latched on the falling edge of CK (for the transmitter) and are read on the rising
edge (for the receiver). The WS signal is also latched on the falling edge of CK.
CK
WS
SD
This mode needs two write or read operations to/from the SPIx_DR register.
• In transmission mode:
If 0x8EAA33 has to be sent (24-bit):
•
In reception mode:
If data 0x8EAA33 is received:
810/874
2
Figure 319. I S Philips protocol waveforms (16/32-bit full accuracy)
CK
WS
SD
MSB
2
Figure 320. I S Philips standard waveforms (24-bit frame)
Transmission
24-bit data
MSB
Channel left 32-bit
Figure 321. Transmitting 0x8EAA33
First write to Data register
0x8EAA
transmission reception
Can be 16-bit or 32-bit
Channel left
Reception
8-bit remaining 0 forced
LSB
Second write to Data register
Only the 8 MSBs are sent
to compare the 24 bits.
8 LSBs have no meaning
RM0366 Rev 5
LSB MSB
Channel
right
Channel right
0x33XX
and can be anything
RM0366
MS19591V1
MS19592V1
MS19593V2