ST STM32F301 6 Series Reference Manual page 49

RM0366
3.2.3 Flash program and erase operations
The STM32F3xx embedded flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the flash
memory, using the JTAG, SWD protocol or the bootloader to load the user application into
the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, I
programming data into memory. IAP allows the user to reprogram the flash memory while
the application is running. Nevertheless, part of the application has to have been previously
programmed in the flash memory using ICP.
The reprogram and erase operations are managed through the following seven flash
registers:
•
Key register (FLASH_KEYR)
•
Option byte key register (FLASH_OPTKEYR)
•
Flash control register (FLASH_CR)
•
Flash status register (FLASH_SR)
•
Flash address register (FLASH_AR)
•
Option byte register (FLASH_OBR)
•
Write protection register (FLASH_WRPR)
An on going flash memory operation does not block the CPU as long as the CPU does not
access the flash memory.
On the contrary, during a program/erase operation to the flash memory, any attempt to read
the flash memory stalls the bus. The read operation proceeds correctly once the
program/erase operation has completed. This means that code or data fetches cannot be
made while a program/erase operation is ongoing.
For program and erase operations on the flash memory (write/erase), the internal RC
oscillator (HSI) must be ON.
Unlocking the flash memory
After reset, the FPEC is protected against unwanted write or erase operations. The
FLASH_CR register is not accessible in write mode, except for the OBL LAUNCH bit, used
to reload the OBL. An unlocking sequence should be written to the FLASH_KEYR register
to open the access to the FLASH_CR register. This sequence consists of two write
operations into FLASH_KEYR register:
1. Write KEY1 = 0x45670123
2. Write KEY2 = 0xCDEF89AB
Any wrong sequence locks up the FPEC and the FLASH_CR register until the next reset.
In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated. This is done after the first write cycle if KEY1 does not match, or during the
second write cycle if KEY1 has been correctly written but KEY2 does not match.
The FPEC and the FLASH_CR register can be locked again by user software by writing the
LOCK bit in the FLASH_CR register to 1.
RM0366 Rev 5
Embedded flash memory
2
C, SPI, etc.) to download
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