ST STM32F301 6 Series Reference Manual page 701

RM0366
Bit 25 AUTOEND: Automatic end mode (controller mode)
Note: This bit has no effect in target mode or when the RELOAD bit is set.
Bit 24 RELOAD: NBYTES reload mode
Bits 23:16 NBYTES[7:0]: Number of bytes
Note: Changing these bits when the START bit is set is not allowed.
Bit 15 NACK: NACK generation (target mode)
Note: Writing 0 to this bit has no effect.
Bit 14 STOP: STOP condition generation
Note: Writing 0 to this bit has no effect.
Bit 13 START: START condition generation
Note: Writing 0 to this bit has no effect.
This bit is set and cleared by software.
0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are
transferred.
This bit is set and cleared by software.
0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR
flag is set when NBYTES data are transferred, stretching SCL low.
The number of bytes to be transmitted/received is programmed there. This field is don't care
in target mode with SBC = 0.
The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP
condition or an Address matched is received, or when PE = 0.
0: an ACK is sent after current received byte.
1: a NACK is sent after current received byte.
This bit is used only in target mode: in controller receiver mode, NACK is automatically
generated after last byte preceding STOP or RESTART condition, whatever the NACK
bit value.
When an overrun occurs in target receiver NOSTRETCH mode, a NACK is
automatically generated, whatever the NACK bit value.
When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value
does not depend on the NACK value.
This bit only pertains to controller mode. It is set by software and cleared by hardware when
a STOP condition is detected or when PE = 0.
0: No STOP generation
1: STOP generation after current byte transfer
This bit is set by software. It is cleared by hardware after the START condition followed by
the address sequence is sent, by an arbitration loss, by a timeout error detection, or when
PE = 0. It can also be cleared by software, by setting the ADDRCF bit of the I2C_ICR
register.
0: No START generation
1: RESTART/START generation:
If the I2C is already in controller mode with AUTOEND = 0, setting this bit generates a
repeated START condition when RELOAD = 0, after the end of the NBYTES transfer.
Otherwise, setting this bit generates a START condition once the bus is free.
The START bit can be set even if the bus is BUSY or I2C is in target mode.
This bit has no effect when RELOAD is set.
Inter-integrated circuit interface (I2C)
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