ST STM32F301 6 Series Reference Manual page 282

Digital-to-analog converter (DAC1)
13.5.4 DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which possible
events will trigger conversion as shown in
TIM6_TRGO event
Reserved
Reserved
TIM15_TRGO event
TIM2_TRGO event
Reserved
EXTI line9
SWTRIG
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is
selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only
one APB1 clock cycle.
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Table 46. External triggers (DAC1)
Source
Internal signal from on-chip
timers
External pin
Software control bit
RM0366 Rev 5
Table 46.
Type
RM0366
TSEL[2:0]
000
001
010
011
100
101
110
111