ST STM32F301 6 Series Reference Manual page 763

RM0366
Bit 5 LBDL: LIN break detection length
This bit is for selection between 11 bit or 10 bit break detection.
0: 10-bit break detection
1: 11-bit break detection
This bit can only be written when the USART is disabled (UE=0).
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Please refer
to
Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the USART is disabled (UE=0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bits 3:0 Reserved, must be kept at reset value.
Note: The 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.
26.8.3 USART control register 3 (USART_CR3)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
OVRDI
DEP DEM DDRE
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TCBGTIE: Transmission complete before guard time interrupt enable
Note: If smartcard mode is not supported, this bit is reserved and must be kept at reset value
Bit 23 Reserved, must be kept at reset value.
Bit 22 WUFIE: Wake-up from Stop mode interrupt enable
Note: WUFIE must be set before entering in Stop mode.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Section 26.4: USART implementation on page
28 27 26 25
Res. Res. Res.
12 11 10 9
ONEBI
CTSIE CTSE
S T
rw rw rw rw
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TCBGT=1 in the USART_ISR register.
(see Section 26.4: USART
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever WUF=1 in the USART_ISR register
The WUF interrupt is active only in Stop mode.
If the USART does not support the wake-up from Stop feature, this bit is reserved and
must be kept at reset value.
714.
24 23 22
TCBGT
Res. WUFIE WUS1
IE
rw rw
8 7 6
RTSE DMAT DMAR SCEN
rw rw rw
implementation).
RM0366 Rev 5
21 20 19 18
SCARC SCARC
WUS0
NT2 NT1
rw rw rw rw
5 4 3 2
NACK HDSEL IRLP
rw rw rw rw
17 16
SCARC
Res.
NT0
rw
1 0
IREN EIE
rw rw
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