ST STM32F301 6 Series Reference Manual page 855

RM0366
DBGMCU_CR
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 DBG_STANDBY: Debug Standby mode
Bit 1 DBG_STOP: Debug Stop mode
Bit 0 DBG_SLEEP: Debug Sleep mode
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector
(except a few status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and
HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU
generate a system reset during Standby mode so that exiting from Standby is identical than
fetching from reset
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including
HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the
one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently,
the software must reprogram the clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are
provided by the internal RC oscillator which remains active in STOP mode. When exiting
STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal,
etc. (in the same way it would do in case of DBG_STOP=0)
0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as
previously configured by the software while HCLK is disabled.
In Sleep mode, the clock controller configuration is not reset and remains in the previously
programmed state. Consequently, when exiting from Sleep mode, the software does not
need to reconfigure the clock controller.
1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same
clock that is provided to FCLK (system clock as previously configured by the software).
24 23 22 21
Res Res Res Res
8 7 6 5
Res Res. Res.
RM0366 Rev 5
Debug support (DBG)
20 19 18 17
Res Res Res Res
4 3 2 1
DBG_
DBG_
Res. Res STAND
STOP
BY
rw rw
16
Res
0
DBG_
SLEEP
rw
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