ST STM32F301 6 Series Reference Manual page 838

Debug support (DBG)
The Cortex
•
SWJ-DP: Serial wire/JTAG debug port
•
AHP-AP: AHB access port
•
ITM: Instrumentation trace macrocell
•
FPB: Flash patch breakpoint
•
DWT: Data watchpoint trigger
•
TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
It also includes debug features:
• Flexible debug pinout assignment
•
MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on the debug feature supported by the Cortex
the Cortex
Kit-r0p1 TRM (see
28.2 Reference Arm documentation
•
Cortex
It is available from: http://infocenter.arm.com
•
Arm® Debug Interface V5
• Arm® CoreSight™ Design Kit revision r0p1 Technical Reference Manual
28.3 SWJ debug port (serial wire and JTAG)
The STM32F3xx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an Arm
standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and an SW-DP
(2-pin) interface.
•
The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port.
•
The serial wire debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
838/874
®
-M4F core provides integrated on-chip debug support. It is composed of:
®
-M4 with FPU-r0p1 Technical Reference Manual and to the CoreSight™ Design
Section 28.2: Reference Arm
®
-M4F r0p1 Technical Reference Manual (TRM)
documentation).
RM0366 Rev 5
RM0366
®
-M4F core, refer to