ST STM32F301 6 Series Reference Manual page 702

Inter-integrated circuit interface (I2C)
Bit 12 HEAD10R: 10-bit address header only read direction (controller receiver mode)
Note: Changing this bit when the START bit is set is not allowed.
Bit 11 ADD10: 10-bit addressing mode (controller mode)
Note: Changing this bit when the START bit is set is not allowed.
Bit 10 RD_WRN: Transfer direction (controller mode)
Note: Changing this bit when the START bit is set is not allowed.
Bits 9:0 SADD[9:0]: Target address (controller mode)
Note: Changing these bits when the START bit is set is not allowed.
25.9.3 I2C own address 1 register (I2C_OAR1)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait states, except if a write access occurs while a write access is ongoing. In
this case, wait states are inserted in the second write access until the previous one is
completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
31 30 29
Res. Res. Res. Res.
15 14 13
OA1EN Res. Res. Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 OA1EN: Own address 1 enable
Bits 14:11 Reserved, must be kept at reset value.
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0: The controller sends the complete 10-bit target address read sequence: START + 2 bytes
10-bit address in write direction + RESTART + first seven bits of the 10-bit address in read
direction.
1: The controller sends only the first seven bits of the 10-bit address, followed by read
direction.
0: The controller operates in 7-bit addressing mode
1: The controller operates in 10-bit addressing mode
0: Controller requests a write transfer
1: Controller requests a read transfer
Condition: In 7-bit addressing mode (ADD10 = 0):
SADD[7:1] must be written with the 7-bit target address to be sent. Bits SADD[9], SADD[8]
and SADD[0] are don't care.
Condition: In 10-bit addressing mode (ADD10 = 1):
SADD[9:0] must be written with the 10-bit target address to be sent.
28 27 26 25
Res. Res. Res.
12 11 10 9
OA1M
Res.
ODE
rw rw
0: Own address 1 disabled. The received target address OA1 is NACKed.
1: Own address 1 enabled. The received target address OA1 is ACKed.
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
RM0366 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OA1[9:0]
rw rw rw rw
RM0366
17 16
Res. Res.
1 0
rw rw