ST STM32F301 6 Series Reference Manual page 667

RM0366
Figure 257. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1
Read I2C_RXDR.RXDATA
Example I2C target receiver 3 bytes, NOSTRETCH = 0:
RXNE
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd data3
Example I2C target receiver 3 bytes, NOSTRETCH = 1:
RXNE
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
No
I2C_ISR.RXNE
=1?
Yes
Figure 258. Transfer bus diagrams for I2C target receiver
(mandatory events only)
ADDR
Address data1
S A
EV1
RXNE
S Address data 1
A A
RM0366 Rev 5
Inter-integrated circuit interface (I2C)
Target reception
Target initialization
No
RXNE
RXNE
data2
A A
EV2 EV3
RXNE RXNE
data 2 data 3
A
EV2
EV1 EV3
I2C_ISR.STOPF
=1?
Yes
Set I2C_ICR.STOPCF
Legend
RXNE
data3
A
EV4
Legend
P
A
MSv19856V3
Transmission
Reception
SCL stretch
Transmission
Reception
SCL stretch
MSv19857V5
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