ST STM32F301 6 Series Reference Manual page 97

RM0366
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. Select this mode by setting the LSEBYP and LSEON bits in the
register (RCC_BDCR). The external clock signal (square, sinus, or triangle) with ~50% duty
cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See
Figure 12.
7.2.5 LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) and RTC. The clock frequency is around 40
kHz (between 30 kHz and 50 kHz). For more details, refer to the electrical characteristics
section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
(RCC_CSR).
The LSIRDY flag in the
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the
7.2.6 System clock (SYSCLK) selection
Three different clock sources can be used to drive the system clock (SYSCLK):
• HSI oscillator
•
HSE oscillator
•
PLL
After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source, which is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the
control register (RCC_CR)
used as a system clock.
7.2.7 Clock security system (CSS)
Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1 and
TIM15/16/17) and an interrupt is generated to inform the software about the failure (Clock
Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI
is linked to the Cortex
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI is executed indefinitely unless the CSS interrupt pending
bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by
setting the CSSC bit in the
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
Control/status register (RCC_CSR)
indicate which clock(s) is (are) ready and which clock is currently
®
-M4F NMI (non-maskable interrupt) exception vector.
Clock interrupt register
RM0366 Rev 5
Reset and clock control (RCC)
indicates if the LSI oscillator is
Clock interrupt register
(RCC_CIR).
RTC domain control
Control/status register
(RCC_CIR).
Clock
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