Interrupts and events
11.3.6
Pending register (EXTI_PR1)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
Res.
PR30
Res.
Res.
rc_w1
15
14
13
PR15
PR14
PR13
PR12
rc_w1
rc_w1
rc_w1
rc_w1
Bits 29:23 Reserved, must be kept at reset value.
Bits 20:19 PRx: Pending bit on line x (x = 20 to 19)
Bits 17:0 PRx: Pending bit on line x (x = 17 to 0)
188/874
28
27
26
25
Res.
Res.
Res.
12
11
10
9
PR11
PR10
PR9
rc_w1
rc_w1
rc_w1
Bit 31 Reserved, must be kept at reset value.
Bit 30 PRx: Pending bit on line x (x = 30)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by writing a '1' to the bit.
Bit 22 PRx: Pending bit on line x (x = 22)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by writing a '1' to the bit.
Bit 21 Reserved, must be kept at reset value.
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by writing a '1' to the bit.
Bit 18 Reserved, must be kept at reset value.
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by writing a '1' to the bit.
24
23
22
Res.
Res.
PR22
Res.
rc_w1
8
7
6
PR8
PR7
PR6
PR5
rc_w1
rc_w1
rc_w1
rc_w1
RM0366 Rev 5
21
20
19
18
PR20
PR19
Res.
rc_w1
rc_w1
5
4
3
2
PR4
PR3
PR2
rc_w1
rc_w1
rc_w1
RM0366
17
16
PR17
PR16
rc_w1
rc_w1
1
0
PR1
PR0
rc_w1
rc_w1
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