ST STM32F301 6 Series Reference Manual page 635

RM0366
24.6.11 RTC shift control register (RTC_SHIFTR)
This register is write protected. The write access procedure is described in
write protection on page 611.
Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
ADD1S Res. Res. Res.
w
15 14 13
Res.
w w
Bit 31 ADD1S: Add one second
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to effectively
add a fraction of a second to the clock in an atomic operation.
Bits 30:15 Reserved, must be kept at reset value.
Bits 14:0 SUBFS[14:0]: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since this
counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
28 27 26 25
Res. Res. Res.
12 11 10 9
w w w w
sure that the shadow registers have been updated with the shifted time.
24 23 22
Res. Res. Res.
8 7 6
SUBFS[14:0]
w w w
RM0366 Rev 5
Real-time clock (RTC)
RTC register
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
w w w w
17 16
Res. Res.
1 0
w w
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