ST STM32F301 6 Series Reference Manual page 856

Debug support (DBG)
28.15.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
The DBGMCU_APB1_FZ register is used to configure the MCU under DEBUG. It concerns
the APB1 peripherals:
•
Timer clock counter freeze
•
I2C SMBUS timeout freeze
•
Window watchdog and independent watchdog counter freeze support
This DBGMCU_APB1_FZ is mapped on the external PPB bus at address 0xE0042008.
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address: 0xE004 2008
Only 32-bit access is supported.
Power on reset (POR): 0x0000 0000 (not reset by system reset)
31 30
15 14
Bits 31 Reserved, must be kept at reset value.
Bit 30 DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 29:25 Reserved, must be kept at reset value.
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
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RM0366 Rev 5
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