ST STM32F301 6 Series Reference Manual page 730

Universal synchronous/asynchronous receiver transmitter (USART/UART)
26.5.5 Tolerance of the USART receiver to clock deviation
The asynchronous receiver of the USART works correctly only if the total clock system
deviation is less than the tolerance of the USART receiver. The causes which contribute to
the total deviation are:
•
DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter's local oscillator)
•
DQUANT: Error due to the baud rate quantization of the receiver
•
DREC: Deviation of the receiver's local oscillator
•
DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
where
DWU is the error due to sampling point deviation when the wake-up from Stop mode is
used.
when M[1:0] = 01:
when M[1:0] = 00:
when M[1:0] = 10:
t
WUUSART
–
–
The USART receiver can receive data correctly at up to the maximum tolerated
deviation specified in
•
9-, 10- or 11-bit character length defined by the M bits in the USART_CR1 register
• Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
•
Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.
• Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register.
730/874
DTRA + DQUANT + DREC
is the time between:
The detection of start bit falling edge
The instant when clock (requested by the peripheral) is ready and reaching the
peripheral and regulator is ready.
Table 102
<
+ DTCL + DWU USART receiver' s tolerance
t
WUUSART
DWU = -------------------------- -
×
11 Tbit
t
WUUSART
DWU
= -------------------------- -
×
10 Tbit
t
WUUSART
DWU
= -------------------------- -
×
9 Tbit
and Table 103 depending on the following choices:
RM0366 Rev 5
RM0366