ST STM32F301 6 Series Reference Manual page 93

RM0366
I2S_CKIN
HSI RC
/2,/3,...
/16
OSC_OUT
4-32 MHz
HSE OSC
OSC_IN
OSC32_IN
LSE OSC
32.768kHz
OSC32_OUT
MCO
Main clock
1. For full details about the internal and external clock source characteristics, refer to the "Electrical characteristics" section in
your device datasheet.
2. TIM1 can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB or APB2
subsystem clocks are not divided by more than 2 cumulatively.
3. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4).
When the programmable factor is '1', the AHB prescaler must be equal to '1'.
Figure 11. STM32F3xx clock tree
HSI
8 MHz
/2
PLLSRC
SW
PLLMUL
HSI
PLL
PLLCLK
x2,x3,..
x16
HSE
CSS
/32
RTCCLK
LSE
RTCSEL[1:0]
LSI
IWDGCLK
LSI RC
to IWDG
40kHz
PLLNODIV
MCOPRE
/1,2 PLLCLK
HSI
/1,2,4,
LSI
.. 128
HSE
SYSCLK
LSE
output
MCO
HSI
SYSCLK
I2SSRC
SYSCLK
to I2Sx (x = 2,3)
Ext. clock
HCLK
/8
AHB APB1
AHB
PCLK1
prescaler
prescaler
/1,2,..512 /1,2,4,8,16
SYSCLK
If (APB1 prescaler
=1) x1 else x2
APB2
PCLK2
prescaler
/1,2,4,8,16
to RTC
If (APB2 prescaler
=1) x1 else x2
ADC
Prescaler
/1,2,4
ADC
Prescaler
/1,2,4,6,8,10,12,16,
32,64,128,256
RM0366 Rev 5
Reset and clock control (RCC)
FLITFCLK
to Flash programming interface
to I2Cx (x = 1,2,3)
to AHB bus, core,
memory and DMA
to cortex System timer
FHCLK Cortex free
running clock
to APB1 peripherals
to TIM 2, 6, 7
PCLK1
SYSCLK
to USART1
HSI
LSE
to APB2 peripherals
TIM1,15,16,17
x2
to ADC1
MS32660V4
93/874
125