ST STM32F301 6 Series Reference Manual page 553

RM0366
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit field defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
19.5.18 TIM15 DMA address for full transfer (TIM15_DMAR)
Address offset: 0x4C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
19.5.19 TIM15 register map
TIM15 registers are mapped as 16-bit addressable registers as described in the table
below:
Register
Offset
name
TIM15_CR1
0x00
Reset value
TIM15_CR2
0x04
Reset value
TIM15_SMCR
0x08
Reset value
12 11 10 9
rw rw rw rw
(TIMx_CR1 address) + (DBA + DMA index) x 4
Table 69. TIM15 register map and reset values
General-purpose timers (TIM15/TIM16/TIM17)
8 7 6
DMAB[15:0]
rw rw rw
0
RM0366 Rev 5
5 4 3 2
rw rw rw rw
CKD
[1:0]
0 0 0 0
MMS[2:0]
0 0 0 0 0 0
TS[2:0]
0 0 0
1 0
rw rw
0 0 0 0
0 0 0 0
SMS[2:0]
0 0 0 0
553/874
574