ST STM32F301 6 Series Reference Manual page 808

Serial peripheral interface / integrated interchip sound (SPI/I2S)
The I2S shares three common pins with the SPI:
•
SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in half-duplex mode only).
•
WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
•
CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
•
I2S2ext_SD and I2S3ext_SD: additional pins (mapped on the MISO pin) to control the
I2S full-duplex mode.
An additional pin can be used when a master clock output is needed for some external
audio devices:
•
MCK: Master Clock (mapped separately) is used, when the I2S is configured in master
mode (and when the MCKOE bit in the SPIx_I2SPR register is set), to output this
additional clock generated at a preconfigured frequency rate equal to 256 × f
I2S modes, and to 128 x f
frequency.
The I2S uses its own clock generator to produce the communication clock when it is set in
master mode. This clock generator is also the source of the master clock output. Two
additional registers are available in I
configuration SPIx_I2SPR and the other one is a generic I2S configuration register
SPIx_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock
polarity, etc.).
The SPIx_CR1 register and all CRC registers are not used in the I
SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are
not used.
The I2S uses the same SPI register for data transfer (SPIx_DR) in 16-bit wide mode.
27.7.2 I2S full duplex
To support I2S full-duplex mode, two extra I2S instances called extended I2Ss (I2S2_ext,
I2S3_ext) are available in addition to I2S2 and I2S3 (see
duplex interface is consequently based on I2S2 and I2S2_ext, and the second one on I2S3
and I2S3_ext.
Note: I2S2_ext an I2S3_ext are used only in full-duplex mode.
1. Where x can be 2 or 3.
808/874
S
Figure 318. I2S full-duplex block diagram
I2Sx_SCK
I2S_WS
for all PCM modes, where f
2
S mode. One is linked to the clock generator
SPI/I2Sx
I2Sx_ext
RM0366 Rev 5
is the audio sampling
S
2
S mode. Likewise, the
Figure 318). The first I2S full-
SPIx_MOSI/I2Sx_SD(in/out)
I2Sx_extSD(in/out)
RM0366
for all
S
MS19910V2