ST STM32F301 6 Series Reference Manual page 807

RM0366
27.7 I2S functional description
27.7.1 I2S general description
The block diagram of the I2S is shown in
MOSI/SD
MISO/
I2S2ext_SD/
I2S3ext_SD (1)
NSS/WS
CK
I2SMOD
MCK
1. I2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I2S full-duplex mode.
The SPI can function as an audio I2S interface when the I2S capability is enabled (by
setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same
pins, flags and interrupts as the SPI.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
Figure 317. I2S block diagram
Master control logic
SPI
baud rate generator
I2S_ CK
Figure 317.
Address and data bus
Tx buffer
BSY OVR MODF
16-bit
Shift register
16-bit
Rx buffer
I2SCFG
[1:0]
Bidi Bidi
mode OE
LSB
SPE BR2 BR1 BR0 MSTR CPOL CPHA
First
2
I S clock generator
MCKOE ODD I2SDIV[7:0]
RM0366 Rev 5
CRC CH
UDR
ERR SIDE
LSB first
CK CH
I2SSTD DATLEN
LEN
[1:0]
[1:0]
POL
I2S
MOD I2SE
CRC CRC Rx
DFF SSM SSI
EN Next only
I2SxCLK
FRE
TxE RxNE
Communication
control
MS19909V1
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