ST STM32F301 6 Series Reference Manual page 251

RM0366
12.5.4 ADC configuration register (ADCx_CFGR, x=1)
Address offset: 0x0C
Reset value: 0x0000 00000
31 30 29
Res. AWD1CH[4:0]
rw rw
15 14 13
AUT OVR
Res. CONT
DLY MOD
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection
These bits are set and cleared by software. They select the input channel to be guarded by the analog
watchdog.
00000: reserved (analog input channel 0 is not mapped)
00001: ADC analog input channel-1 monitored by AWD1
.....
10010: ADC analog input channel-18 monitored by AWD1
others: reserved, must not be used
Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers.
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 25 JAUTO: Automatic injected group conversion
This bit is set and cleared by software to enable/disable automatic injected group conversion after
regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no regular nor injected conversion is ongoing).
Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels
This bit is set and cleared by software
0: Analog watchdog 1 disabled on injected channels
1: Analog watchdog 1 enabled on injected channels
Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected
conversion is ongoing).
Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels
This bit is set and cleared by software
0: Analog watchdog 1 disabled on regular channels
1: Analog watchdog 1 enabled on regular channels
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
28 27 26 25
JAUTO
rw rw rw rw
12 11 10 9
EXTEN[1:0]
rw rw rw rw
24 23 22
JAWD1 AWD1 AWD1S
EN EN GL
rw rw rw
8 7 6
EXTSEL[3:0] ALIGN
rw rw rw
RM0366 Rev 5
Analog-to-digital converters (ADC)
21 20 19 18
JDISC
JQM DISCNUM[2:0]
EN
rw rw rw rw
5 4 3 2
RES[1:0] Res.
rw rw rw
17 16
DISC
EN
rw rw
1 0
DMA DMA
CFG EN
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