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RM0366
31
30
29
Res.
Res.
Res.
Res.
15
14
13
CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
w
w
w
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 CTEIF7: Transfer error flag clear for channel 7
Bit 26 CHTIF7: Half transfer flag clear for channel 7
Bit 25 CTCIF7: Transfer complete flag clear for channel 7
Bit 24 CGIF7: Global interrupt flag clear for channel 7
Bit 23 CTEIF6: Transfer error flag clear for channel 6
Bit 22 CHTIF6: Half transfer flag clear for channel 6
Bit 21 CTCIF6: Transfer complete flag clear for channel 6
Bit 20 CGIF6: Global interrupt flag clear for channel 6
Bit 19 CTEIF5: Transfer error flag clear for channel 5
Bit 18 CHTIF5: Half transfer flag clear for channel 5
Bit 17 CTCIF5: Transfer complete flag clear for channel 5
Bit 16 CGIF5: Global interrupt flag clear for channel 5
Bit 15 CTEIF4: Transfer error flag clear for channel 4
Bit 14 CHTIF4: Half transfer flag clear for channel 4
Bit 13 CTCIF4: Transfer complete flag clear for channel 4
Bit 12 CGIF4: Global interrupt flag clear for channel 4
Bit 11 CTEIF3: Transfer error flag clear for channel 3
Bit 10 CHTIF3: Half transfer flag clear for channel 3
Bit 9 CTCIF3: Transfer complete flag clear for channel 3
Bit 8 CGIF3: Global interrupt flag clear for channel 3
Bit 7 CTEIF2: Transfer error flag clear for channel 2
Bit 6 CHTIF2: Half transfer flag clear for channel 2
Bit 5 CTCIF2: Transfer complete flag clear for channel 2
Bit 4 CGIF2: Global interrupt flag clear for channel 2
Bit 3 CTEIF1: Transfer error flag clear for channel 1
Bit 2 CHTIF1: Half transfer flag clear for channel 1
Bit 1 CTCIF1: Transfer complete flag clear for channel 1
Bit 0 CGIF1: Global interrupt flag clear for channel 1
28
27
26
25
CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5
w
w
w
12
11
10
9
w
w
w
w
Direct memory access controller (DMA)
24
23
22
w
w
w
8
7
6
w
w
w
RM0366 Rev 5
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
17
16
w
w
1
0
w
w
167/874
174
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