ST STM32F301 6 Series Reference Manual page 215

RM0366
Example:
•
JDISCEN=1, channels to be converted = 1, 2, 3
–
–
–
–
Note: When all injected channels have been converted, the next trigger starts the conversion of
the first injected channel. In the example above, the 4th trigger reconverts the 1st injected
channel 1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously:
the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
12.3.21 Queue of context for injected conversions
A queue of context is implemented to anticipate up to 2 contexts for the next injected
sequence of conversions.
This context consists of:
•
Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL[3:0] in
ADCx_JSQR register)
•
Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADCx_JSQR register)
All the parameters of the context are defined into a single register ADCx_JSQR and this
register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of
parameters:
•
The JSQR register can be written at any moment even when injected conversions are
ongoing.
•
Each data written into the JSQR register is stored into the Queue of context.
•
At the beginning, the Queue is empty and the first write access into the JSQR register
immediately changes the context and the ADC is ready to receive injected triggers.
•
Once an injected sequence is complete, the Queue is consumed and the context
changes according to the next JSQR parameters stored in the Queue. This new
context is applied for the next injected sequence of conversions.
•
A Queue overflow occurs when writing into register JSQR while the Queue is full. This
overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the
write access of JSQR register which has created the overflow is ignored and the queue
of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.
•
Two possible behaviors are possible when the Queue becomes empty, depending on
the value of the control bit JQM of register ADCx_CFGR:
–
–
1st trigger: channel 1 converted (a JEOC event is generated)
2nd trigger: channel 2 converted (a JEOC event is generated)
3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated
...
If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be
empty during run operations: the Queue always maintains the last active context
and any further valid start of injected sequence will be served according to the last
active context.
If JQM=1, the Queue can be empty after the end of an injected sequence or if the
Queue is flushed. When this occurs, there is no more context in the queue and
both injected software and hardware triggers are disabled. Therefore, any further
RM0366 Rev 5
Analog-to-digital converters (ADC)
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