ST STM32F301 6 Series Reference Manual page 203

RM0366
Software procedure to enable the ADC
1. Set ADEN=1.
2. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done
using the associated interrupt (setting ADRDYIE=1).
Note: ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle after the ADCAL bit is
cleared by hardware(end of the calibration).
Software procedure to disable the ADC
1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is
ongoing. If required, stop any regular and injected conversion ongoing by setting
ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0.
2. Set ADDIS=1.
3. If required by the application, wait until ADEN=0, until the analog ADC is effectively
disabled (ADDIS will automatically be reset once ADEN=0).
ADEN
ADRDY
ADDIS
ADC
state
by S/W
12.3.10 Constraints when writing the ADC control bits
The software is allowed to write the RCC control bits to configure and enable the ADC clock
(refer to RCC Section), the control bits DIFSEL in the ADCx_DIFSEL register and the
control bits ADCAL and ADEN in the ADCx_CR register, only if the ADC is disabled (ADEN
must be equal to 0).
The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of
the ADCx_CR register only if the ADC is enabled and there is no pending request to disable
the ADC (ADEN must be equal to 1 and ADDIS to 0).
Figure 30. Enabling / Disabling the ADC
t
STAB
OFF Startup RDY
by H/W
RM0366 Rev 5
Analog-to-digital converters (ADC)
Converting CH
RDY
REQ
OFF
-OF
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