ST STM32F301 6 Series Reference Manual page 30

List of figures
Figure 45. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 221
Figure 46. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 221
Figure 47. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 222
Figure 48. Example of JSQR queue of context when changing SW and HW triggers. . . . . . . . . . . . 222
Figure 49. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 50. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 51. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 52. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 53. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 54. Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 55. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 56. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 57. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 58. AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 233
Figure 59. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 60. AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . .
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 61. AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 235
Figure 62. AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 63. Analog watchdog's guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 64. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 238
Figure 65. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . . . . . . . . . . . 239
Figure 66. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 239
Figure 67. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 239
Figure 68. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 69. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 70. DAC1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 71. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 72. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 281
Figure 73. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 74. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 283
Figure 75. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 76. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 284
Figure 77. Comparator 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 78. Comparator 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 79. Comparator 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 80. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 81. Comparator and operational amplifier
connections
Figure 82. Timer controlled Multiplexer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 83. Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 84. Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 85. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . . 308
Figure 86. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 87. TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 88. Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Figure 89. Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 90. Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 91. Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 92. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
30/874
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
RM0366 Rev 5
RM0366