ST STM32F301 6 Series Reference Manual page 153

RM0366
10.3 DMA implementation
10.3.1 DMA1
DMA1 is implemented with the hardware configuration parameters shown in the table below.
Number of channels
10.3.2 DMA request mapping
DMA controller
The hardware requests from the peripherals (TIMx (x=1, 2, 15..17), ADC1, SPI[2,3], I2Cx
(x=1..3), DAC_Channel1 and USARTx (x=1..3)) are simply logically ORed before entering
the DMA. This means that on one channel, only one request must be enabled at a time (see
Figure 20).
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Caution: A same peripheral request can be assigned to two different channels only if the application
ensures that these channels are not requested to be served at the same time. In other
words, if two different channels receive a same asserted peripheral request at the same
time, an unpredictable DMA hardware behavior occurs.
Table 24
Table 23. DMA implementation
Feature
lists the DMA requests for each channel.
Direct memory access controller (DMA)
RM0366 Rev 5
DMA
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