ST STM32F301 6 Series Reference Manual page 651

RM0366
Internal signal name Signal type
i2c_ker_ck
i2c_pclk
i2c_it
i2c_rx_dma
i2c_tx_dma
25.4.3 I2C clock requirements
The I2C kernel is clocked by I2CCLK.
The I2CCLK period t
t
I2CCLK
t
I2CCLK
where t
LOW
analog and digital filter delays (when enabled).
The digital filter delay is DNF[3:0] x t
The PCLK1 clock period t
SCL period.
Caution: When the I2C kernel is clocked by PCLK1, this clock must respect the conditions for t
25.4.4 I2C mode selection
The peripheral can operate as:
• Target transmitter
•
Target receiver
• Controller transmitter
•
Controller receiver
By default, the peripheral operates in target mode. It automatically switches from target to
controller mode upon generating START condition, and from controller to target mode upon
arbitration loss or upon generating STOP condition. This allows the use of the I2C
peripheral in a multicontroller I²C-bus environment.
Communication flow
In controller mode, the I2C peripheral initiates a data transfer and generates the clock
signal. Serial data transfers always begin with a START condition and end with a STOP
condition. Both START and STOP conditions are generated in controller mode by software.
In target mode, the peripheral recognizes its own 7-bit or 10-bit address, and the general
call address. The general call address detection can be enabled or disabled by software.
The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The address is contained in
the first byte (7-bit addressing) or in the first two bytes (10-bit addressing) following the
START condition. The address is always transmitted in controller mode.
Table 83. I2C internal input/output signals
Input
Input
Output
Output
Output
must respect the following conditions:
I2CCLK
< (t - t ) / 4
LOW filters
< t
HIGH
is the SCL low time, t
HIGH
must respect the condition t
PCLK
RM0366 Rev 5
Inter-integrated circuit interface (I2C)
I2C kernel clock, also named I2CCLK in this document
I2C APB clock
I2C interrupts, refer to Table 97
I2C receive data DMA request (I2C_RX)
I2C transmit data DMA request (I2C_TX)
is the SCL high time, and t
.
I2CCLK
Description
for the list of interrupt sources
is the sum of the
filters
< 4/3 t , where t
PCLK SCL
is the
SCL
.
I2CCLK
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