ST STM32F301 6 Series Reference Manual page 34

List of figures
Figure 245. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Figure 246. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Figure 247. I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Figure 248. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Figure 249. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 250. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Figure 251. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 252. Target initialization flow
Figure 253. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . . . . . . . . . . . . 663
Figure 254. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . . . . . . . . . . . . 664
Figure 255. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . . . . . . . . 665
Figure 256. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . . . . . . . . . . . . . . 666
Figure 257. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . . . . . . . . . . . . . . 667
Figure 258. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Figure 259. Controller clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Figure 260. Controller initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Figure 261. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Figure 262. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Figure 263. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . . . . . . . . . . . . . 673
Figure 264. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . . . . . . . . . . . . . 674
Figure 265. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Figure 266. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . . . . . . . . . . . . . . 677
Figure 267. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . . . . . . . . . . . . . . . 678
Figure 268. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Figure 269. Timeout intervals for t
Figure 270. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . . . . . . . . . . . . 687
Figure 271. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . . . . . . . . . . . . . . . . . . 687
Figure 272. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . . . . . . . . . . . . . . 689
Figure 273. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . . . . . . . . . . . . . . . . . . . 690
Figure 274. Bus transfer diagrams for SMBus controller transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Figure 275. Bus transfer diagrams for SMBus controller receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Figure 276. USART block diagram
Figure 277. Word length programming
Figure 278. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 279. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Figure 280. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Figure 281. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 282. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 283. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Figure 284. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Figure 285. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 737
Figure 286. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 738
Figure 287. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Figure 288. USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Figure 289. USART data clock timing diagram (M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Figure 290. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Figure 291. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 292. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Figure 293. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
34/874
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
, t
LOW:SEXT LOW:MEXT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
RM0366 Rev 5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
RM0366