ST STM32F301 6 Series Reference Manual page 840

Debug support (DBG)
28.4.1 SWJ debug port pins
Five pins are used as outputs from the STM32F3xx for the SWJ-DP as alternate functions of
general-purpose I/Os. These pins are available on all packages.
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
NJTRST
28.4.2 Flexible SWJ-DP pin assignment
After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, it is possible to disable some or all of the SWJ-DP ports and so, to release (in gray
in the table below) the associated pins for general-purpose I/O(GPIO) usage. For more
details on how to disable SWJ-DP port pins, please refer to
function multiplexer and
Full SWJ (JTAG-DP + SW-DP) - Reset State
Full SWJ (JTAG-DP + SW-DP) but without NJTRST
JTAG-DP Disabled and SW-DP Enabled
JTAG-DP Disabled and SW-DP Disabled
28.4.3 Internal pull-up and pull-down on JTAG pins
It is necessary to ensure that the JTAG input pins are not floating since they are directly
connected to flip-flops to control the debug mode features. Special care must be taken with
the SWCLK/TCK pin, which is directly connected to the clock of some of these flip-flops.
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Table 113. SWJ debug port pins
JTAG debug port
Type Description
JTAG Test Mode
I
Selection
I JTAG Test Clock
I JTAG Test Data Input
O JTAG Test Data Output
I JTAG Test nReset
mapping.
Table 114. Flexible SWJ-DP pin assignment
Available debug ports
RM0366 Rev 5
SW debug port
Type Debug assignment
Serial Wire Data
IO
Input/Output
I Serial Wire Clock
- -
TRACESWO if async trace
-
is enabled
- -
Section 8.3.2: I/O pin alternate
SWJ IO pin assigned
PA13 / PA14 /
PA15 /
JTMS/ JTCK/
JTDI
SWDIO SWCLK
X X X
X X X
X X
Released
RM0366
Pin
assign
ment
PA13
PA14
PA15
PB3
PB4
PB3 / PB4/
JTDO NJTRST
X X
X