ST STM32F301 6 Series Reference Manual page 234

Analog-to-digital converters (ADC)
Figure 60. AUTODLY=1, regular HW conversions interrupted by injected conversions
Regular trigger
ADC state
RDY
EOC
EOS
ADC_DR
read access
ADC_DR
Injected trigger
JEOS
ADC_JDR1
ADC_JDR2
by SW
1. AUTDLY=1
2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3.
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6
234/874
(DISCEN=1, JDISCEN=1)
Ignored
DLY
CH1 CH2
RDY
regular
regular
DLY (CH1) DLY (CH2)
D1
by HW
Not ignored (occurs during
injected sequence)
DLY CH5 RDY CH6
RDY
injected injected
D2
Ignored
RM0366 Rev 5
CH3 RDY CH1
DLY
regular
regular
DLY (CH1)
DLY (CH3)
D3
Ignored
DLY (inj)
D5
D6
Indicative timings
RM0366
DLY RDY CH2
regular
D1
MS31022V1