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Advanced-control timer (TIM1)
Bits 31:0 DMAB[31:0]: DMA register for burst accesses
17.4.23
TIM1 option registers (TIM1_OR)
Address offset: 0x50
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 1:0 TIM1_ETR_ADC1_RMP[1:0]: TIM1_ETR_ADC1 remapping capability
Note: ADC1 AWD is 'ORed' with the other TIM1_ETR source signals. It is consequently
17.4.24
TIM1 capture/compare mode register 3
(TIM1_CCMR3)
Address offset: 0x54
Reset value: 0x0000 0000
The channels 5 and 6 can only be configured in output.
Output compare mode:
31
30
29
Res.
Res.
Res.
Res.
15
14
13
OC6
OC6M[2:0]
CE
rw
rw
rw
420/874
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
00: TIM1_ETR is not connected to any AWD
01: TIM1_ETR is connected to ADC1 AWD1
10: TIM1_ETR is connected to ADC1 AWD2
11: TIM1_ETR is connected to ADC1 AWD3
necessary to disable by software other sources (input pins).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
OC6
OC6FE
Res.
PE
rw
rw
rw
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
OC6M[3]
Res.
Res.
rw
8
7
6
OC5
Res.
OC5M[2:0]
CE
rw
rw
RM0366 Rev 5
20
19
18
Res.
Res.
Res.
4
3
2
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
OC5PE OC5FE
rw
rw
rw
rw
RM0366
17
16
Res.
Res.
1
0
TIM1_ETR_ADC1_
RMP
rw
rw
17
16
Res.
OC5M[3]
rw
1
0
Res.
Res.
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