ST STM32F301 6 Series Reference Manual page 697

RM0366
25.7 I2C DMA requests
25.7.1 Transmission using DMA
DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit
of the I2C_CR1 register. Data is loaded from an SRAM area configured through the DMA
peripheral (see
register whenever the TXIS bit is set.
Only the data are transferred with DMA.
In controller mode, the initialization, the target address, direction, number of bytes and
START bit are programmed by software (the transmitted target address cannot be
transferred with DMA). When all data are transferred using DMA, DMA must be initialized
before setting the START bit. The end of transfer is managed with the NBYTES counter.
Refer to
In target mode:
•
With NOSTRETCH = 0, when all data are transferred using DMA, DMA must be
initialized before the address match event, or in ADDR interrupt subroutine, before
clearing ADDR.
•
With NOSTRETCH = 1, the DMA must be initialized before the address match event.
The PEC transfer is managed with the counter associated to the NBYTES[7:0] bitfield. Refer
to SMBus target transmitter
Note: If DMA is used for transmission, it is not required to set the TXIE bit.
25.7.2 Reception using DMA
DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit of
the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area
configured through the DMA peripheral (refer to
controller
transferred with DMA.
In controller mode, the initialization, the target address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, DMA
must be initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter.
In target mode with NOSTRETCH = 0, when all data are transferred using DMA, DMA must
be initialized before the address match event, or in the ADDR interrupt subroutine, before
clearing the ADDR flag.
The PEC transfer is managed with the counter associated to the NBYTES[7:0] bitfield. Refer
to SMBus target receiver
Note: If DMA is used for reception, it is not required to set the RXIE bit.
25.8 I2C debug modes
When the device enters debug mode (core halted), the SMBus timeout either continues
working normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT bits in the
DBG block.
Section 10: Direct memory access controller
Controller transmitter.
and
(DMA)) whenever the RXNE bit is set. Only the data (including PEC) are
and SMBus controller
Inter-integrated circuit interface (I2C)
SMBus controller transmitter.
Section 10: Direct memory access
receiver.
RM0366 Rev 5
(DMA)) to the I2C_TXDR
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