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ST STM32F301 6 Series Reference Manual page 816

Advanced arm-based 32-bit mcus

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Serial peripheral interface / integrated interchip sound (SPI/I2S)
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
dum: not significant data
In slave mode, the user has to enable the audio interface before the WS becomes active.
This means that the I2SE bit must be set to 1 when WS = 1 for I
WS = 0 for other standards.
816/874
Figure 336. Start sequence in master mode
Master I2S Philips Standard
dum
Left sample
Master I2S MSB or LSB justified
dum
Left sample
Master PCM short frame
dum
Sample1
Master PCM long frame
dum
Sample1
RM0366 Rev 5
RM0366
Right sample
Right sample
Sample 2
Sample 2
MSv37520V2
2
S Philips standard, or when

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