ST STM32F301 6 Series Reference Manual page 362

Advanced-control timer (TIM1)
PWM edge-aligned mode
•
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at '1'. If the compare value is 0 then OCxRef is held at '0'.
Figure 126
TIMx_ARR=8.
CCRx=4
CCRx=8
CCRx>8
CCRx=0
•
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 341
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at '1'. 0% PWM
is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
'00' (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
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shows some edge-aligned PWM waveforms in an example where
Figure 126. Edge-aligned PWM waveforms (ARR=8)
Counter register 0
OCXREF
CCxIF
OCXREF
CCxIF
OCXREF '1'
CCxIF
OCXREF '0'
CCxIF
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MS31093V1