ST STM32F301 6 Series Reference Manual page 676

Inter-integrated circuit interface (I2C)
Controller receiver
In the case of a read transfer, the RXNE flag is set after each byte reception, after the eighth
SCL pulse. An RXNE event generates an interrupt if the RXIE bit of the I2C_CR1 register is
set. The flag is cleared when I2C_RXDR is read.
If the total number of data bytes to receive is greater than 255, select the reload mode, by
setting the RELOAD bit of the I2C_CR2 register. In this case, when the NBYTES[7:0]
number of data bytes is transferred, the TCR flag is set and the SCL line is stretched low
until NBYTES[7:0] is written with a non-zero value.
When RELOAD = 0 and he number of data bytes defined in NBYTES[7:0] is transferred:
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In automatic end mode (AUTOEND = 1), a NACK and a STOP are automatically sent
after the last received byte.
•
In software end mode (AUTOEND = 0), a NACK is automatically sent after the last
received byte. The TC flag is set and the SCL line is stretched low in order to allow
software actions:
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A RESTART condition can be requested by setting the START bit of the I2C_CR2
register, with the proper target address configuration and the number of bytes to
transfer. Setting the START bit clears the TC flag and sends the START condition
and the target address on the bus.
A STOP condition can be requested by setting the STOP bit of the I2C_CR2
register. This clears the TC flag and sends a STOP condition on the bus.
RM0366 Rev 5
RM0366