ST STM32F301 6 Series Reference Manual page 111

RM0366
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
Bits 10:5 Reserved, must be kept at reset value.
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
Bits 31 Reserved, must be kept at reset value.
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
7.4.6 AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29
Res. Res. Res. ADC1EN
15 14 13
Res. Res. Res.
0: No effect
1: Reset SPI3 and I2S3
0: No effect
1: Reset SPI2 and I2S2
0: No effect
1: Reset window watchdog
0: No effect
1: Reset TIM6
0: No effect
1: Reset TIM2
28 27 26 25
Res. Res. Res.
rw
12 11 10 9
Res. Res. Res. Res.
24 23 22
GPIOF
TSCEN Res. Res..
EN
rw rw
8 7 6
CRC
Res. Res. Res.
EN
rw
RM0366 Rev 5
Reset and clock control (RCC)
21 20 19 18
GPIOD GPIOC GPIOB
EN EN EN
rw rw rw
5 4 3 2
FLITF SRAM
Res.
EN EN
rw rw
17 16
GPIOA
Res.
EN
rw
1 0
DMA1
Res.
EN
rw
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